用于并网逆变器的带宽限制PLL设计及其稳定性保证

In power grids, the phase locked loop (PLL) device is utilized to align the phase of a voltage source inverter (VSI) with that of its terminal grid-bus. As conventional PLLs are affected in transients by frequency and phase deviations, the adverse impact often results in unstable situations. To that end, a novel robust synchronization mechanism is proposed to substantially enhance the classical PLL performance. The main properties of the proposed scheme, characterized as bandwidth limiting-(BaLi) PLL, are theoretically established by conducting a small-signal analysis and by deriving criteria that guarantee system stability. Additionally, an effective parameter tuning methodology is deployed in detail that compensates the influence of the filter and the power line parameters on the synchronization process. As shown in the paper, the whole design offers an effective tool with clear abilities to limit the PLL bandwidth in a desired interval and to achieve fast and accurate synchronization with the grid-bus voltage. To evaluate the response and stability properties of the BaLi-PLL, experimental scenarios for the proposed and other state-of-the-art PLLs are examined. The BaLi-PLL indicates a significantly improved response, under different hard disturbances, thus verifying its robust and efficient performance.