SiC MOSFET中动态开关应力的解耦效应

This study conducts a comparative analysis of the Threshold Voltage (Vth) degradation in Silicon Carbide (SiC) MOSFETs subjected to various dynamic tests in accordance with industry guidelines. To ensure a fair comparison, a custom experimental setup is employed. The observed degradation outcomes show variability depending on whether high voltage levels were applied, driving conditions or switching events occurrence. A comprehensive explanation of the experimental observations is provided by means of Finite Element Method (FEM) simulations and parasitic capacitances analysis. Furthermore, the study introduces a conceptual framework and methodology facilitating the emulation of high-voltage aging effects through simplified degradation test procedures.