1.2 kV 4H-SiC MOSFET在重复短路测试下静态与动态特性的退化机制

Abstract In this paper, repetitive short-circuit (RSC) tests are conducted at off-state and on-state gate-source voltages ( V GS,OFF / V GS,ON ) of −4/+15 V, −4/+19 V and 0/+19 V, respectively, to investigate the degradation behaviors of 1.2 kV 4H-SiC MOSFETs. Combining experimental and simulation results, it is found that trapped electrons or holes in the gate oxide during the avalanche process are the main degradation mechanism for the static parameters. This results in increases of 0.4 V and 3.0 mΩ in V TH and R DS,ON , respectively, at V GS,OFF / V GS,ON = −4/+19 V; 0.45 V and 4.1 mΩ at V GS,OFF / V GS,ON = 0/+19 V; and decreases of 0.69 V and 3.2 mΩ at V GS,OFF / V GS,ON = −4/+15 V after 240 short-circuit (SC) tests. The dynamic characteristics of the device under test, including C GS , C DS , C GD also degrade. The trapped holes in the gate oxide above the JFET region lead to a thinner depletion region and an obvious increase in C GD . Furthermore, the gate leakage current under high reverse gate bias is affected by the RSC tests, primarily attributed to trapped electrons hopping to the poly-Si/SiO 2 interface via defect states.