1.2-kV平面SiC MOSFET在重复UIS应力作用下阈值电压的演变

Abstract In this paper, repetitive unclamped inductive switching (UIS) stressing was conducted on 1.2-kV planar silicon carbide (SiC) MOSFETs . Different off-state gate voltage biases ( V gs-off = 0 V/−5 V/−10 V) were applied. The evolution of on-resistance ( R on ) and threshold voltage ( V th ) in different conditions has been observed. It was found that R on was increased and V th was negatively shifted for −5 V and −10 V V gs-off conditions. Failure analysis was conducted to investigate the R on degradation mechanism. Aluminum (Al) melting on chip upper surface occurred during UIS stressing, which was verified by scanned-electron-beam observation. Regarding V th shift, the repetitive UIS stressing applied on the devices was analyzed as a combination of high-temperature reverse bias (HTRB) stress and high-temperature gate bias (HTGB) stress. To aid the mechanism analysis, TCAD simulations of the UIS avalanche process were conducted. When negative V gs-off was applied, the channel region entered an accumulated state, and the electric field was directed toward the gate oxide. This facilitated hot hole injection into the gate oxide, leading to a significant increase in positive oxide charge density. As the magnitude of the negative V gs-off bias increased, the electric field stress in the gate oxide and hole density in the channel region were aggravated, resulting in a more pronounced V th shift.