不同P阱离子注入设计对1.2kV SiC MOSFET体二极管第三象限导通退化特性的影响研究

This work systematically investigates how different P-well ion implantation designs affect the third-quadrant conduction characteristics and the surge reliability of 1.2kV SiC MOSFETs. Four P-well structures (P-well A to P-well D) are designed by adjusting peak concentration and implantation depth in order to construct P-well resistance and source-drain current transport. The experimental results demonstrate a decline in surge capability with an increase in P-well resistance. The highest degradation rate reached is 7.8% in P-well A, while P-well D exhibited the least change, at 4.7%. When VGS = 0V, the parallel conduction path formed by the channel and the body diode reduces differences in source-drain voltage drop caused by P-well design. Turning off the channel further reduces the surge capability. Repetitive surge current tests reveal that the accumulation of trapped holes and thermo-mechanical fatigue in the package are the main causes of device degradation. Furthermore, deep energy level defects induced by high-energy ion implantation form localized barriers by trapping carriers, thereby triggering bipolar degradation and reducing surge reliability.