SOI n-p-n双栅TFET中物理局域化界面陷阱的统计变异性

Interface trap reliability in MOS devices is a significant area of concern in the domain of semiconductor devices. With the advent of new device architectures with miniaturized dimensions, it has become fundamentally important to include methods to predict interface trap reliability. This article reports the impact of interface traps on the low power performance of tunnel field-effect transistors (TFETs) through statistical variability approach. Tunnel field-effect transistors (TFETs), which function via quantum mechanical tunnelling, have emerged as promising devices for low-power applications. Interface traps are localized energy states at the semiconductor-oxide interface that can trap charge carriers, and affect the low-power performance of the devices. These traps can be either acceptor-like or donor-like based on their position within the energy band gap. This article investigates the impact of these traps on the key performance metrics of a silicon-on-insulator (SOI) n-p-n double-gate TFET (DG TFET). Calibrated with experimental data, the proposed work involves 200 simulations using technology computer-aided design tool, Sentaurus TCAD. Considering Gaussian distribution of interface traps, the traps were physically localized at the interface, where a trap-localized region was 4 nm long. At a time, one trap-localized region was considered, which was randomly placed in each of the 200 simulations. The variations in the threshold voltage ( \({V}_{th}\) ), on-current ( \({I}_{\text{ON}}\) ), and off-current ( \({I}_{\text{OFF}}\) ) are represented through the standard deviation of the parameters. Since the methodology adopted in this work is universal, it has the potential to be a promising technique to assess the reliability of any kind of MOS device in an unbiased manner.