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1.2-kV平面栅与沟槽栅SiC MOSFET在体二极管重复脉冲电流应力下的退化研究

Investigation on Degradation of 1.2-kV Planar and Trench SiC MOSFETs Under Repetitive Pulse Current Stress of Body Diode

作者 Hengyu Yu · Michael Jin · Jiashu Qian · Monikuntala Bhattacharya · Shiva Houshmand · Limeng Shi
期刊 IEEE Transactions on Power Electronics
出版日期 2025年6月
技术分类 储能系统技术
技术标签 储能系统 SiC器件 工商业光伏 可靠性分析
相关度评分 ★★★★ 4.0 / 5.0
关键词 碳化硅MOSFET 体二极管可靠性 双极退化 基面位错 TCAD模拟
语言:

中文摘要

本文首次通过实验研究了最新商用 1.2 千伏碳化硅(SiC)平面栅、增强型对称沟槽和非对称沟槽结构金属氧化物半导体场效应晶体管(MOSFET)的体二极管可靠性。所提出的测试平台通过重复脉冲电流模式,可在合理的热限制内实现大电流测试。实验结果揭示了大面积 1.2 千伏商用 SiC MOSFET 存在双极退化风险。对退化现象和机制进行了表征与分析,包括由衬底产生的基面位错(BPD)导致的第一象限和第三象限特性退化,以及由制造工艺产生的 BPD 导致的第三象限膝点电压($V_{\text{on}}$)和阻断电压退化。具体而言,确定了两个退化阶段:在初始应力阶段,导通电阻($R_{\text{ds}}$)、第三象限导通压降($V_{\text{sd}}$)和漏电流($I_{dss}$)显著增加。然而,经过一定时间后,退化趋于饱和,$R_{ds}$、$V_{sd}$和$I_{dss}$不再进一步恶化。此外,采用技术计算机辅助设计(TCAD)仿真对增强型对称沟槽 MOSFET 的双极退化行为进行建模,特别着重分析和验证 BPD 定位对器件性能的影响。另外,还深入研究了壳温、电流密度和芯片面积对双极退化的影响。在大面积器件中,制造工艺引发的 BPD 在高温和高电流密度下更容易被激活,从而导致$R_{ds}$、$V_{sd}$和$I_{dss}$退化。相比之下,小面积器件中$R_{ds}$、$V_{sd}$和$I_{dss}$的轻微退化归因于衬底产生的 BPD。

English Abstract

This article experimentally investigates the body diode reliability of the latest commercial 1.2-kV silicon carbide (SiC) mosfets with planar-gate, reinforced symmetric-trench, and asymmetric-trench structures for the first time. The proposed testing platform enables testing at high currents within reasonable thermal limits through a repetitive pulse current mode. Experimental results reveal a risk of bipolar degradation in large-area 1.2-kV commercial SiC mosfets. Degradation phenomena and mechanisms, including first-quadrant and third-quadrant characteristics degradation caused by basal plane dislocations (BPDs) originating from the substrate, as well as third-quadrant knee voltage ( V_on ) and blocking voltage degradation resulting from BPDs originating from fabrication processes, are characterized and analyzed. Specifically, two degradation phases were identified: during the initial stress period, on-resistance ( R_ds ), third-quadrant on-voltage drop ( V_sd ), and leakage current ( I_dss ) exhibited significant increases. However, after a certain period, the degradation saturated, and R_ds,,V_sd,,and,I_dss ceased to further deteriorate. Furthermore, technology computer-aided design (TCAD) simulations were employed to model the bipolar degradation behavior in reinforced symmetric-trench mosfets, with particular emphasis on analyzing and validating the impact of BPDs localization on device performance. In addition, the effects of case temperature, current density, and chip area on bipolar degradation are thoroughly examined. In large-area devices, BPDs induced by fabrication processes are more easily activated under high temperature and high current density, leading to degradation in R_ds,,V_sd,,and,I_dss . In contrast, slight degradation in R_ds,,V_sd,,and,I_dss in small-area devices is attributed to BPDs originating from the substrate.
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SunView 深度解读

从阳光电源的业务视角来看,这项关于1.2kV SiC MOSFET体二极管可靠性的研究具有重要的战略意义。SiC功率器件是我们光伏逆变器和储能变流器的核心部件,其可靠性直接影响系统的长期稳定运行和全生命周期成本。

该研究揭示的双极退化风险对我们的产品设计具有重要警示作用。在实际应用中,逆变器和储能系统频繁经历续流工作模式,体二极管承受重复脉冲电流应力。研究发现的两阶段退化特性——初期导通电阻、正向压降和漏电流显著增加,随后趋于饱和——为我们制定器件选型标准和老化测试方案提供了科学依据。特别是大面积器件在高温高电流密度下更易激活制造工艺引入的基面位错,这直接关联到我们大功率产品(如1500V光伏逆变器、MW级储能PCS)的可靠性设计。

论文对比的三种结构(平面栅、加强型对称沟槽、非对称沟槽)的性能差异,为我们优化供应链和定制化器件规格提供了技术参考。研究采用的重复脉冲测试方法和TCAD仿真验证,可以借鉴到我们的器件验证流程中,提升产品可靠性预测能力。

技术挑战在于如何在保证性能的前提下,通过优化开关策略、热管理和并联均流设计来减轻体二极管应力。机遇则在于,深入理解退化机理后,我们可以与上游供应商协同开发低BPD密度的定制化SiC器件,或通过智能控制算法主动规避高风险工况,从而在竞争中建立差异化的可靠性优势,特别是在要求25年以上寿命的光伏和储能应用场景中。