基于自适应体偏置技术的数字LDO稳压器以改善瞬态响应

Abstract This paper introduces an adaptive body biasing (ABB) technique for improving the transient response of the Digital Low-Dropout regulator (DLDO) during events of step increment in the load current demand. The proposed ABB technique detects voltage undershoot and dynamically tunes the body bias of the pMOSFETs in the DLDO’s switching array to reduce its threshold voltage , thereby boosting the current supply to help meet the transient load demand. With an ABB-integrated DLDO, designed and simulated in a 28 nm FDSOI (RVT) process, we achieve a reduction in the peak output voltage undershoot and recovery time by 21.23 % and 41.13 %, respectively, compared to DLDO operation without ABB. To validate our approach in the bulk CMOS process, we also designed the ABB-integrated DLDO in a 180 nm bulk process and reported a reduction in the peak output voltage undershoot and recovery time by 13.69 % and 43.8 %, respectively. The robustness of the design to mismatches and process variations is justified via Monte-Carlo simulations, indicating the reliable performance of the proposed ABB technique in DLDO.