高K介质包裹GaN环栅场效应管在IoT系统中的高频器件设计与分析

Gallium Nitride (GaN)-based Gate Stack (GS) Gate-All-Around Field Effect Transistors (GAA FETs) are promising candidates for next-generation energy-efficient electronics due to their exceptional material properties, such as high electron mobility, wide bandgap, and superior thermal stability. This study focuses on the performance evaluation of GaN-based GAA FETs for both DC and AC explorations incorporating high-k dielectric spacers and source/drain underlap engineering. The DC analyses parameters such as subthreshold slope, threshold voltage, drain current, leakage current and current ratio. ~95% reduction in off-state leakage current and ~606% increase in switching ratio is acquired in comparison to proposed 2nm technology node IRDS2025. Additionally, the subthreshold swing is optimized around ~65mV/decade indicating superior leakage control and switching performance. AC analysis evaluates key figures of merits, including transconductance, cut-off frequency, and parasitic capacitances. It is observed that the high-k spacer significantly enhances electrostatic control reducing short-channel effects (SCEs) and improving device stability. The optimized underlap minimizes parasitic capacitance, leading to ~103% increase in cut-off frequency and ~163% improvement in transconductance, resulting in enriched high-frequency performance. These findings underscore the potential of GaN-based GAA FETs with high-k spacer and underlap designs for low-power, high-speed applications in green and sustainable electronics, particularly for IoT systems and 5G technologies. The integration of gate underlap with high-k dielectric spacer region effectively reduces SCEs and parasitic resistances. By controlling the electric field distribution and improving electrostatics integrity this design achieves augmented switching speed while suppresses leakage significantly, making the device a strong candidate for next-generation digital and RF applications.