采用外部吸收电容与升压电容的SiC JFET/Si IGBT级联器件开关可控性

Silicon insulated gate bipolar transistor (Si IGBT) is a crucial device in high-power systems. However, the enormous switching loss ( E_ SW ) has always been the primary problem that limits its applications. To reduce E_ SW , inspired by the SiC JFET/Si MOSFET cascode (SSMC), a SiC JFET and low-voltage Si IGBT cascode (L.SSIC) is proposed and validated by experiment and technology computer-aided design (TCAD) simulation. In the on-state, due to the bipolar conduction mode, the L.SSIC has stronger current conductivity than the SSMC. However, the tail current ( I_ tail ) is still serious during the turn-off transient. To optimize the switching transient and eliminate I_ tail , an absorption capacitor ( C_ A ) and a boost capacitor ( C_ B ) are adopted in L.SSIC. Through switch characteristic testing, the proposed L.SSIC with C_ A and C_ B is verified. The research results show that E_ SW of L.SSIC is 42.5% lower than that of conventional Si IGBT at 600 V/60 A. At a current of 80 A and switching frequency of 200 kHz, the power loss of L.SSIC is 26.8% and 6.9% lower than that of the silicon carbide (SiC) MOSFET and SSMC, respectively. In addition, in boost circuit testing, under a duty cycle of 70% and working current of 20 A, the L.SSIC achieves similar conversion efficiency to SiC MOSFET. The advantage becomes more apparent as the operating current increases.