通过三维共封装和增强的dv/dt控制能力释放GaN/SiC级联器件的全部潜力

To unlock the full fast-switching potential of the GaN-HEMT/SiC-JFET cascode device, parasitic interconnection inductances are minimized with a 3-D stacked co-packaging configuration. This configuration offers the benefits of reduced switching loss and suppressed oscillation. Equipped with the 3-D co-package configuration, the dv/dt control capability of the GaN/SiC cascode device is enhanced by introducing an additional gate-drain capacitor, CGD-LV, to the low-voltage GaN HEMT. This additional CGD-LV improves the coupling between the input control gate voltage and the JFET's gate voltage, which ultimately determines the switching speed of the GaN/SiC cascode device. Experimental results verified the GaN/SiC cascode device, when equipped with the 3-D co-packaged configuration and the additional CGD-LV, demonstrated fast switching capability with adequate dv/dt control.