智能功率集成电路衬底电流的仿真、分析与布局优化验证

Today circuit failures in Smart Power ICs due to substrate couplings are partially addressed during the circuit design phase. The state-of-the-art guidelines for the optimization of parasitic couplings provide mainly qualitative rules, which are difficult to implement and to verify during the design of a complex Smart Power circuit. These rules are often based on the physical device simulations or...