基于实时前馈控制的多电平选择性栅极驱动器

This article presents a multilevel, real-time feedforward control-based selective gate driver (SGD) strategy that uses a single digital signal to achieve 64-level turn-on and 64-level turn-off gate resistance selections to improve the inverter performance reflected at the system level. The feedforward control is based on the inverter operating conditions and implemented on a pulsewidth modulation (PWM) switching-cycle level. The proposed SGD effectively minimizes switching energy loss while maintaining the drain-source voltage overshoot within the required limit, without necessitating ultrafast dynamic control within a subswitching cycle time frame, which typically lasts tens of microseconds. Four different time-based simulation models are used to simulate the influence of gate resistance and the benefits of SGD during switching transients, switching cycles, fundamental cycles, and driving cycles. The hardware for the proposed SGD has been designed and tested in a single-phase full-bridge (SPFB) inverter. A fundamental cycle-based simulation and experimental results between the conventional gate driver (CGD) and SGD are shown to verify the switching loss savings achieved by SGD in an SPFB inverter. A driving cycle-based analysis demonstrates a significant fuel economy improvement with the proposed SGD method in an electric vehicle (EV), compared to the CGD.