晶圆上100-V p-GaN HEMT动态导通电阻与阈值电压漂移分析：模拟单片集成半桥电路

In this paper, we present electrical characterization data concerning the degradation of critical device parameters (threshold voltage, VTH, and on-state resistance, RON) of 100- V p-GaN HEMTs to be employed in monolithically integrated half-bridge circuits. To this purpose, a custom characterization setup emulating the stress conditions of either the Low Side (LS) or High Side (HS) device was realized. This was necessary as the LS device degrades only during the OFF-state condition, whereas the HS device degrades also during the ON-state as a consequence of the finite source-to-body voltage. In either configuration, the device is periodically switched on and off (Ts = 10 μs and tON = 2 μs) for up to 1000 s and both VTH and RON are monitored for several decades to determine the time evolution of the parameters. The interpretation of experimental results was aided by calibrated device numerical simulations. We found that both LS and HS device have the same VTH and RON dynamics, but the HS device experiences a larger degradation of both parameters due to the back-gating effect. Characterization performed at different substrate temperature (T) revealed an activation energy of ≈0.7 eV for both VTH and RON transients, which is signature of hole emission from C-related buffer traps. Furthermore, hole leakage current from the Schottky gate during ON-state was found to be beneficial as it partially compensates the building up of negative charges in buffer.