低泄漏全垂直式GaN-on-Si功率MOSFET

We demonstrate fully-vertical GaN-on-Si power MOSFETs with state-of-the-art OFF-state characteristics, based on a 7.6 _μ_ m thick NPN epitaxial structure grown on 6-inch low-resistance Si substrates with conductive buffer layers. This fully-vertical configuration eliminates the commonly used n+-GaN drain contact layer underneath the n--GaN drift region and effectively alleviates the undesired Si-dopant induced tensile stress during GaN growth, which provides sufficient design space for a 7 _μ_ m thick n--GaN drift layer on Si and leads to a high breakdown voltage of 567 V defined at a low OFF-state drain current density of 1 mA/cm2 from the fabricated devices. Enhancement mode operation with a threshold voltage of 4.2 V is also observed, along with a low specific ON-resistance ( _RON,SP_) of 7.8 mΩ⋅cm2 and a high ON-state current density of 8 kA/cm2. The results demonstrate a promising approach to realizing high-performance fully-vertical transistors on cost-effective Si substrates and