碳化硅MOSFET在漏极应力下的动态阈值电压漂移

Silicon carbide (SiC) MOSFETs are widely favored for their excellent performance. However, reliability concerns have hindered their rapid development, with threshold voltage drift being one of the key concerns. Although threshold voltage drift under static and dynamic gate stress has been widely investigated, limited attention has been paid to the threshold voltage drift induced by drain stress. In this work, a dedicated test platform for SiC MOSFETs was developed, enabling independent and decoupled application of gate and drain stresses. Moreover, the drain stress can be further decomposed into voltage and current components for more detailed analysis. In addition, TCAD simulations were used to investigate the mechanisms underlying the different threshold voltage drifts induced by various stress modes. It was found that drain stress has a noticeable effect on threshold voltage drift, which cannot be neglected. Moreover, there is a coupling effect between drain and gate stresses. These findings aim to provide better management and coping strategies for threshold voltage drift in power electronic device applications.