精度可重构的近似加法器设计

Arithmetic circuits such as adders are fundamental components in implementing image processing applications. Since these applications are error-tolerant, the adders can be approximated to improve their PDP (Power-Delay-Product) metric while maintaining accuracy within tolerance limits. This paper proposes a segmentation technique to design ternary approximate adders, where the entire adder chain is split into segments, with the intent to reduce the delay. Next, for applications that require tunable accuracy, we incorporate a reconfiguration technique in the segmented approximate adders, using a divide-and-conquer methodology that dynamically optimizes the approximate adder’s accuracy, leading to efficient computation. Also, an algorithm was proposed to compute accuracy and hardware complexity in an N-trit accuracy reconfigurable adder. The proposed methodology was validated using an approximate 6-trit adder on its power consumption and delay performance metrics. Compared with the best design in literature, the proposed approximate 6-trit adder exhibits 63% lesser power consumption and 69% lesser delay. The proposed approximate 6-trit adder accuracy was progressively enhanced through the reconfigurable method. After a few reconfiguration stages, the proposed adder matched the accuracy of an exact 6-trit adder while achieving an improved power-delay product (PDP). Finally, the proposed 6-trit adders were validated by using them in the image-blending application.