采用优化平衡寄生电感结构的并联分立式SiC MOSFET三电平T型APF

The implementation of a 100 kVA high-power-density Active Power Filter (APF) with constraints of volume, loss and cost faces the challenges of selecting optimal three-level topology and SiC MOSFET, reducing Turn-off Transient voltage Overshoot (TTVO) and balancing Turn-on Transient Current Sharing (TTCS). This paper presents an optimal solution design methodology for topologies and devices selection, and proposes a parasitic inductance minimized-and-balanced PCB improve method for reducing TTVO and balancing TTCS. The three-level T-type (3LT2) and neutral-point-clamped (NPC) topologies with the finitely enumerated SiC devices are quantitatively evaluated to select the optimal solution satisfying constraints of volume, loss and cost. The 3LT2 circuit with three parallel 1200V discrete devices is evaluated as the optimal solution that faces the TTVO and TTCS problems in practice. A minimized-and-balanced parasitic inductance PCB structure is proposed to solve the challenges. The TTVO is reduced from 1.06 kV to 780 V, a reduction of 26.4 %, and the TTCS deviation from 82.4 % to 3.7 % under an 800 V DC voltage and a 450 A load current. The APF prototype achieves a power density of 4.27 kW/L and a full-load efficiency of 98.16 % with reducing power device cost by 10.4 %.