一种基于氮化镓的低功耗高扇出能力混合逻辑电路

A GaN-based hybrid logic circuit topology is proposed to alleviate trade off relation between transition speed and static power consumption. This circuit topology includes a bootstrap output stage and a CMOS biasing stage, featuring an enhanced driving capability while maintaining the same low static power consumption as the traditional CMOS structures. GaN n/p channel devices are fabricated on a commercial p-GaN cap normally-OFF GaN-on-Si power platform, and their models were extracted. The simulation results show that the proposed hybrid logic circuit could deliver a much higher fan-out capability, and the single-stage driver circuits indicate that the hybrid logic circuit exhibits a stronger current output capability, faster transition speed, and a smaller chip area, compared to traditional CMOS circuits. Furthermore, in multistage driver circuits, the hybrid logic circuit reduces propagation delay by five times without increasing the on-chip area. This design provides an effective solution to the low current density of GaN p-channel devices, paving the way for high-speed, low-power GaN monolithic integrated circuits.