用于PFC整流器的II型电压控制器系数集以最小化直流母线电容

The brief presents a method for deriving a type-II voltage controller coefficients set allowing to minimize the dc link capacitance in single-phase active power factor correction rectifiers (PFCR) operating without hold-up time requirements. The proposed methodology considers grid current quality and dc link voltage loop stability constraints as well as system response to a step-like zero-to-rated load power variation. Design guidelines for deriving the optimal coefficients set and corresponding minimum capacitance value are provided by means of combined time and frequency domain analysis. The findings are accurately supported by simulations and experiments.