基于新型纳米银烧结方法的6英寸晶圆键合实现与评估

Wafer-level power devices, including thyristors, and their derivatives, such as integrated gate-commutated thyristors (IGCTs), demand a higher performance by the electrical transmission system to support society’s development, which poses a significant challenge for thermal management. For these press-pack devices, exerting thermal interface materials (TIMs) is a practical approach to enhance heat dissipation by reducing contact thermal resistance. Considering the electrical conductivity requirement, nanosilver sintering is recognized as an appropriate technique. However, large-area bonding by nanosilver sintering has limited applications owing to more arduous organic emissions and higher thermal stress with the connecting area enlarging. In this study, wafer-level bonding was achieved by employing a tri-layer freestanding film composed of pre-sintered silver and silver foil. A Si wafer was employed to mimic wafer-level devices and to enhance the universality of the process. The introduction of silver foil to partially replace silver paste helps in controlling organic residue. In addition, the film’s structure was designed based on optimization by investigating the effect of the sintered intermediate thickness on the possibility of cracking to prevent failure due to stress. The optimal thickness is identified to be approximately 150~ m. The connectivity quality of the prepared sample was then characterized from macroscale to mesoscale using techniques such as SAM and SEM. Adequate connectivity was confirmed. The shear strength was verified to achieve 135 MPa, substantially higher than 6 MPa regulated in MIL-STD-883K. Finally, the reduction in thermal resistance was comprehensively evaluated using experiments and numerical calculations, and it was estimated to reach 81.24%. In general, the methods for achieving and assessing wafer-level bonding using nanosilver sintering broaden the application of silver sintering and present a template for large-area bonding.