方波电压高频与高dv/dt耦合作用下封装绝缘界面放电特性及绝缘寿命分析

Square voltage coupled high frequency and steep dv/dt is the main cause of interfacial discharge (ID) at the direct bond copper (DBC) substrate of power electronic devices. In this article, a high-frequency partial discharge test system at the junction of ceramic, metal layer, and silicone gel on DBC substrate is built. A partial discharge measurement method capable of shielding from strong electromagnetic interference (EMI) is proposed. The research results show that the rising time is shortened from 500 to 100 ns, and the ID inceptive voltage (IDIV) increases by 13.8%, but it is almost frequency independent. Second, the initial discharge phase is gradually advanced with the shortening of the rising time. The average and maximum discharge amplitude gradually increases and the number of discharges decreases. When the frequency rises from 10 to 50 kHz, the discharge phase percentage increases significantly. While the average discharge amplitude tends to increase and then decrease, the number of discharges increases substantially. Finally, it is found that the frequency is more harmful to the package insulation life than the voltage steepness. The above findings can provide a reference for the high-frequency discharges detection and the package insulation optimization for electronic devices.