一种无电容、无外部时钟、全可综合数字低压差线性稳压器

This article presents an external-clock-free fully synthesizable digital low-dropout regulator (DLDO) without an output capacitor. To lower quiescent current in a steady state, time-based load-state decision is exploited to change an internal clock frequency depending on a load state, while employing a single comparator, a single reference voltage, and a single delay line. In addition, for small v...