模拟控制器中固有时间延迟是不同类型电力电子系统不稳定性的预兆

Inherent time delay-induced instability may manifest as either smooth period-doubling, Hopf or nonsmooth type bifurcations, depending on power circuit topologies, types of controllers, pulse-width modulation schemes and even upon the operating region in parameter space. It has been reported that time delay can induce Hopf bifurcation in dc-ac inverters, as well as period-doubling and nonsmooth bifurcation in dc-dc buck converters. In this paper, the inherent time delay is accounted by first-order Padé approximation in a cumulative way and we obtain rigorous analytical results by combining the Filippov method and Floquet theory. A comparative analysis is carried out for higher order Padé approximations on nonlinear switched model as well as pure time delay on linear averaged model. The results show only 0.03% error in the prediction of bifurcation points. It is also shown that resistive parasitics and inherent time delay arising in the power and control circuit domains, respectively, may act in an opposing and counter-balancing manner to a certain extent. The extent of this naturally occurring compensation depends on the operating zone in parameter space and the type of instability. This knowledge and insight into the shifting patterns of stability boundaries in the parameter space due to time delay and parasitics are vital for good design and reliable operation of power electronic systems. Theoretical predictions are validated by several numerical simulations of the switched model of different topologies and experimental measurements from buck converter. The pure time delay is realized and approximated by a first-order all-pass filter in the experiment.