基于FinFET的逻辑兼容低电压线性注入模拟存储器

This research introduces an advanced analog memory cell architecture based on a floating-gate inverter, implemented in the FinFET technology node. The cell integrates a CMOS logic gate, where its analog levels are directly influenced by the amount of charge stored within the floating gate. This unique shared-floating-gate configuration allows precise control over the stored analog values, making it possible to achieve a wider range of signal levels compared to traditional designs. The complementary design approach further enhances the flexibility and robustness of the memory cell, enabling versatile readout methods that are resilient to variations in process and operating conditions. Additionally, the pulse-controlled modulation of the analog levels, combined with innovative readout techniques tailored to this structure, has been successfully demonstrated in this study, showcasing the potential for high-performance, low-power, and scalable analog memory solutions in future advanced CMOS technologies.