基于55 nm BCD平台的超级分栅LDMOS器件实现优化RSP与79.5% QGD降低，适用于高频xPU电源

In this article, the super split-gate LDMOS (SSG LDMOS) on 55-nm BCD platform is proposed to overcome the tradeoff relationship among breakdown voltage (BV), specific on-resistance ( R _ SP ), and gate-to-drain charge ( Q _ GD ), while satisfying the requirement of high-frequency power system-on-chip (PwrSoC) applications. This device has an ultrashort Gate1 to reach an extremely low Q _ GD and a biased Gate2 to achieve low R _ SP . Measured data confirm an optimal tradeoff between R _ SP and BV for 7–16-V low-voltage device. Significantly, compared with conventional low- C _ GD LDMOS, dynamic performances of 16-V SSG LDMOS show substantial improvements, including a 79.5% reduction in Q _ GD (0.186 nC/mm2) in dc domain and obvious decreases of 89.1% and 71.4% in gate-to-drain capacitance for 0- and 16-V drain voltage, respectively, in the ac domain. These improvements directly benefit high-current dc-dc converter performance. Employing BSIM4-modeled SSG LDMOS, the simulation demonstrates that the efficiency of 89.2% (at 24 A) is achieved for a 5-MHz V _ in~12 – V _ out~1.8 converter. Furthermore, the measured switching figure of merit ( R _ SP Q_ GD ) implies a significant superiority of SSG LDMOS over reported discrete devices and existing BCD technology.