基于阻抗模型的双环控制策略以减少二次谐波电流并提升两级逆变器动态性能

The instantaneous output power of a two-stage single-phase inverter pulsates at twice the output voltage frequency (2fo), which results in a large amount of second harmonic current (SHC) in the front-end dc–dc converter. This article proposes a novel dual-loop control strategy based on the parallel output impedance model of the front-end dc–dc converter, in order to reduce the SHC and improve the dynamic performance. The proportional–integral–resonant controller (PIRC) is used in the current-loop, and the SHC can be further suppressed under the limited loop bandwidth condition. In the voltage-loop, a notch filter is inserted into the forward path of the active disturbance rejection controller (ADRC). It allows the voltage-loop cutoff frequency to become greater than 2fo, which significantly improves the load transient response. Furthermore, a step-by-step closed-loop parameters design method considering the SHC reduction, phase margin, and dynamic performance is proposed. Finally, a 1.8 kW two-stage single-phase inverter prototype is built and tested. The experimental results demonstrate the high effectiveness of the proposed dual-loop control strategy.